***********Lab2*******************
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6. Voltage measured at 01nmos (Vs) is 0.946V
Voltage applied at nmos1 (Vg) is 1.2V (Vdd)
NMOS ON criteria : Vgs>Vth
Or Vg-Vs>Vth
Vs <0.8Vdd
That is, Vs<0.96V
Thus, as 01nmos approaches 0.96V (for this case 0.946V),
the switch turns OFF and limit the voltage to about 0.96V.
Due to MOS characteristic of I3, voltage at 01nmos is limited to one Vth lower than Vdd.
That is, NMOS transmit Logic H with degradation.
Wn=120n
Voltage of nmos1 = 0.946 V (a drop of approximately 0.2*Vdd (=0.24V) compared to the input)
Voltage of nmos2 = 0.891 V
Difference = 0.055 V
Wn=300n
Voltage of nmos1 = 0.959 V (a drop of approximately 0.2*Vdd (=0.24V) to the input)
Voltage of nmos2 = 0.904 V
Difference = 0.055 V
9. R = Rs * L/W, and V = IR
An increase in width will cause R to decrease and hence V to decrease as well.
***********Lab3*******************
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Q3. A smaller C is preferred as T = RC. A smaller C will require a shorter time to charge and discharge.
The preferred load capacitance for this technology is 0.04pF.
Q4. R = Rs L/W and T = RC. With a larger Wp, R will become smaller hence a shorter T.
Q5. Rise time longer than fall time although both transistors are of the same size.
This is due to the mobility of holes being about 2.5 times slower than that of electrons.
Q6. Wp = 270nm will have approximately the same rise and fall time. (0.63n ~ 0.64n)
Ratio = 270/120 = 2.25
(i) tpLH = RC
= 2.5 Rsp * (Lp / Wp) * C
= 2.5 Rsn * (Ln / 2.25Wn) * C
= 1.11 Rsn * (Ln / Wn) * C
(ii) tpHL = RC
= Rsn * (Ln / Wn) * C
(iii) tpLH : tpHL = 1.11 : 1 (within acceptable deviation)
Q7. R = Rs L/W, increase L will cause R to increase. T = RC, with a higher R, T will increase too.
R = Rs L/W, increase W will cause R to decrease. T = RC, with a lower R, T will decrease.
Q8. As Vout is able to swing from 0V to Vdd (full voltage swing) regardless of the ratio of Lp/Wp : Ln/Wn,
hence ratio is not compulsory.
***********Lab4*******************
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12. W = 120n, CAP = 0.04p = 40f
PURE NOR :
Rise = 2.07n Fall = 0.26n (Rise ~= 10 Fall - OK)
Rise occurs when A = B = 0, that is R = 2Rp ~= 5Rn (series)
Fall occurs when A = B = 1, that is R = 0.5Rn (parallel)
13.
(a) A faster performing circuit is preferred over a slower performer.
Hence, we should speed up the rise time instead of depressing the fall time.
(b) A Wp2 = 280n is required.
This is, Wp2 ~= 2.3Wn2 (close to 2.5 times) the difference between Rsn and Rsp.
13. To obtain a rise time ~= fall time for the NOR gate
Wp = 1.2u (120n*10), Wn = 120n, CAP = 40f
The multiplier of 10 is obtained from Q12. It is an approximate factor.
The final size may need to further modify but will be close to the estimated value.
Rise time = 22.85-22.64 = 0.21ns
Fall time = 30.37-30.1 = 0.27ns